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SLG7NT41382 processor power validation SLG7NT41382_ds_r100 rev 1.00 revised november 18, 2016 SLG7NT41382_gp_r001 silego technology, inc. for internal use only this datasheet is for internal use only ? do not distribute ou tside of silego and intel.
silego technology, inc. SLG7NT41382 processor power validation SLG7NT41382_ds_r100 SLG7NT41382_gp_r001 rev 1.00 revised november 18, 2016 general description features ? low power consumption ? pb - free / rohs compliant ? halogen - free ? s t qfn - 20 package output summary ? 1 output ? push pull 2x ? 2 outputs ? open drain pmos 2x pin configuration 1 2 3 4 5 6 7 11 8 9 10 20 19 18 s t q fn - 20 top view 12 13 14 15 16 17 vdd SLG7NT41382 gnd 3.3s_pwrgd 5v_dual_pwrgd 3.3a_pwrgd 1.0a_pwrgd 12s_pwrgd 5s_pwrgd slp_s3_n vr_ready sys_pwrok nc nc rsmrst_n_no_delay socket_present_n fpga_program_ complete_gpio nc nc rsmrst_n rsmrst_pwrgd silego SLG7NT41382 is a low power and small form device. the soc is housed in a 2mm x 3mm stqfn package which is optimal for using with small devices.
page 3 3 processor power validation SLG7NT41382_ds_r100 SLG7NT41382 block diagram
page 4 4 processor power validation SLG7NT41382_ds_r100 SLG7NT41382 p in configuration pin # pin name type pin description 1 vdd pwr supply voltage 2 3.3s_pwrgd digital input digital input without schmitt trigger 3 5v_dual_pwrgd digital input digital input without schmitt trigger 4 3.3a_pwrgd digital input digital input without schmitt trigger 5 1.0a_pwrgd digital input digital input without schmitt trigger 6 12s_pwrgd digital input digital input without schmitt trigger 7 5s_pwrgd digital input digital input without schmitt trigger 8 slp_s3_n digital input digital input wit hout schmitt trigger 9 vr_ready digital input digital input without schmitt trigger 10 sys_pwrok digital output push pull 2x 11 gnd gnd ground 12 nc -- keep floating or connect to gnd 13 nc -- keep floating or connect to gnd 14 rsmrst_n_no_delay digital output open drain pmos 2x 15 socket_present_n digital input digital input without schmitt trigger 16 rsmrst_n digital output open drain pmos 2x 17 rsmrst_pwrgd digital input digital input without schmitt trigger 18 fpga_program_compl ete_gpio digital input digital input w ithout schmitt trigger 19 nc -- keep floating or connect to gnd 20 nc -- keep floating or connect to gnd ordering information part number package type SLG7NT41382v v= s tqfn - 20 SLG7NT41382vtr vtr= s tqfn - 20 ? tape and reel (3k units)
page 5 5 processor power validation SLG7NT41382_ds_r100 SLG7NT41382 absolute maximum conditions parameter min. max. unit v high to gnd - 0.3 7 v voltage at input pins - 0.3 7 v current at input pin - 1.0 1.0 ma storage temperature range - 65 125 c junction temperature -- 150 c esd protection (human body model) 2000 -- v esd protection (charged device model) 13 00 -- v moisture sensitivity level 1 electrical characteristics (@ 25c, unless otherwise stated) symbol parameter condition/note min. typ. max. unit v dd supply voltage 1.71 3.3 5.5 v t a operating temperature - 40 25 85 c i q quiescent current static inputs and outputs -- 1 -- a v o maximal voltage applied to any pin in high - impedance state -- -- vdd v i o maximal average or dc current (note 1) per each chip side (pin2 - pin10, pin12 - pin20) -- -- 90 ma v ih high - level input voltage logic input, at vdd=1.8v 1.10 -- vdd v logic input, at vdd=3.3v 1.78 -- vdd logic input, at vdd=5.0v 2.64 -- vdd v il low - level input voltage logic input, at vdd=1.8v -- -- 0.69 v logic input, at vdd=3.3v -- -- 1.21 logic input, at vdd=5.0v -- -- 1.84 i ih high - level input current logic input pins; v in = vdd - 1.0 -- 1.0 a i il low - level input current logic input pins; v in = 0v - 1.0 -- 1.0 a v oh high - level output voltage push pull & pmos od, i oh = 100ua, 2x driver, at vdd=1.8 v 1.7 1.794 -- v push pull & pmos od, i oh = 3ma, 2x driver, at vdd=3.3 v 2.87 3.21 -- push pull & pmos od, i oh = 5ma, 2x driver, at vdd=5.0 v 4.32 4.89 -- v ol low - level output voltage push pull, i ol = 100ua, 2x driver, at vdd=1.8 v -- 0.004 0.01 v push pull, i ol = 3ma, 2x driver, at vdd=3.3 v -- 0.060 0.108 push pull, i ol = 5ma, 2x driver, at vdd=5.0 v -- 0.076 0.140 i oh high - level output current push pull & pmos od, v oh = v dd - 0.2, 2x driver, at vdd=1.8 v 2.216 3.406 -- ma
page 6 6 processor power validation SLG7NT41382_ds_r100 SLG7NT41382 push pull & pmos od, v oh = 2.4 v, 2x driver, at vdd=3.3 v 11.522 24.16 -- push pull & pmos od, v oh = 2.4 v, 2x driver, at vdd=5.0 v 41.69 68.08 -- i ol low - level output current push pull, v ol =0.15v, 2x driver, at vdd=1.8 v 1.834 3.378 -- ma push pull, v ol =0.4v, 2x driver, at vdd=3.3 v 9.750 16.488 -- push pull, v ol =0.4v, 2x driver, at vdd=5.0 v 13.831 23.16 -- r pull_up internal pull up resistance pull up on pin 15 700 1000 1300 k ? r pull_down internal pull down resistance pull down on pins 2, 3, 4, 5, 6, 7, 8, 9, 17, 18 700 1000 1300 k ? t dly2 delay2 time at temperature 25c 9.02 10.02 10.52 ms at temperature - 40c +85c (note 1) 8.17 10.02 12.45 t su start up time from vdd rising past 1.35v -- 0.3 -- ms 1. guaranteed by design.
page 7 7 processor power validation SLG7NT41382_ds_r100 SLG7NT41382 functionality waveforms d0 ? pin#17 ( rsmrst_pwrgd ) d1 ? pin#18 ( fpga_program_complete_gpio ) d2 ? pin#15 ( socket_present_n ) d3 ? pin#16 ( rsmrst_n) with external 5k ? pull down resistor d4 ? pin#14 ( rsmrst_n_no_delay) with external 5k ? pull down resistor d5 ? pin#2 ( 3.3s_pwrgd ) d6 ? pin#3 ( 5v_dual_pwrgd ) d7 ? pin#4 ( 3.3a_pwrgd ) d8 ? pin#5 ( 1.0a_pwrgd ) d9 ? pin#6 ( 12s_pwrgd ) d10 ? pin#7 ( 5s_pwrgd ) d11 ? pin#8 ( slp_s3_n ) d12 ? pin#9 ( vr_ready ) d13 ? pin#10 ( sys_pwrok ) 1. device functionality
page 8 8 processor power validation SLG7NT41382_ds_r100 SLG7NT41382 package top marking datasheet revision programming code number locked status part code revision date 1.00 001 l 41382 aa 11/18/2016 the ic security bit is locked/set for code security for production unless otherwise specified. revision number is not changed for bit locking .
page 9 9 processor power validation SLG7NT41382_ds_r100 SLG7NT41382 package drawing and dimensions 20 lead s t q fn package jedec mo - 220, variation wece ic net weight: 0.0086 g
page 10 10 processor power validation SLG7NT41382_ds_r100 SLG7NT41382 tape and reel specification package type # of pins nominal package size (mm) max units reel & hub size (mm) trailer a leader b pocket (mm) per reel per box pockets length (mm) pockets length (mm) width pitch s t q fn 20l 2 x3 mm 0.4p green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 carrier tape drawing and dimensions package type pocket btm length (mm) pocket btm width (mm) pocket depth (mm) index hole pitch (mm) pocket pitch (mm) index hole diameter (mm) index hole to tape edge (mm) index hole to pocket center (mm) tape width (mm) a0 b0 k0 p0 p1 d0 e f w s t q fn 20l 2 x3 mm 0.4p green 2.2 3.15 0.76 4 4 1.5 1.75 3.5 8 refer to eia - 481 specifications recommended reflow soldering profile please see ipc/jedec j - std - 020: latest revision for reflow profile based on package volume of 3.3 mm 3 (nominal). more information can be found at www.jedec.org .
page 11 11 processor power validation SLG7NT41382_ds_r100 SLG7NT41382 datasheet revision history date version change 08 / 19 /201 6 0.10 new design for slg46 722 chip 09/12/2016 0.11 updated device revision history 11/16/2016 0.12 locked nvm 11 /18/2016 1.00 production release
page 12 12 processor power validation SLG7NT41382_ds_r100 SLG7NT41382 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding silego green products, please visit our website . our green produc t lines feature: greenpak1 / greenpak2 / greenpak3/ greenpak 4 / greenpak 5: programmable mixed signal matrix product s greenfet1 / greenfet3: mosfet drivers and ultra - small, low rdson load switches greenclk1 / greenclk2 / greenclk3: crystal replacement te chnology products are also available for purchase directly from silego at the silego online store at http://www.silego.com/buy/ . silego technical support datasheets and errata, application notes and example designs, user guides, and hardware support documents and the latest software releases are available at the silego website or can be requested directly at info@silego.com. for specific greenpak design or applications questions and support please send e - mail requests to greenpak@silego.com users of silego products can receive assistance through several channels: contact your local sales representative customers can contact their local sales representative or field application engineer (fae) for support. local sales office s are also available to help customers. more information regarding your local representative is available at th e silego website or send a request to info@silego.com contact silego directly silego can be contacted directly via e - mail at info@silego.com or user submission form, located at the following url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminars and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed and qualified for the consumer market. applications or uses as critical components in life support devices or systems are not authorized. silego technology does n ot assume any liability arising out of such applications or uses of its products. silego technology reserves the right to improve product design, functions and reliability without notice

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